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NT5000

CPU Commander - ROM Emulator

Features

  • The UUT runs unmodified and at full speed
  • No special fixturing is required
  • Only one generic pod is required
  • New processors can be added with just a software update
  • The user needs to know ONLY one high level language set of commands to use the ROM Emulation card
  • No assembly language is required to use the basic functions of the ROM Emulation card
  • Basic functions include Read, Write, RAM test, ROM CHECKSUM, Fill, Copy, Move, etc.
  • Basic diagnostics are available to troubleshoot a dead kernel

General

ROM Emulation is a powerful and versatile method of microprocessor testing. ROM emulation has emerged as the technique of choice for microprocessor test and diagnostic applications. A µP-Based board is tested by replacing the boot ROMs on the Unit Under Test (UUT) with memory emulation pods. Each pod handles 8 bits of the data bus. Processors from 8 to 32 bits can be controlled with 1 to 4 pods (even the most advanced CPUs such as the Intel Pentium generally use only an 8-bit boot path). The emulator takes control of the UUT by re-setting the processor and under the test program's control (monitor program) exercises all functions on the board. Synchronization with the UUT is automatic and requires no additional hardware or connections.

Applications

  • Automatic Test Equipment (ATE)

  • Service and repair work stations

  • Engineering evaluation

  • µP board emulation

Configuration

ROM emulation uses a high level language that enables the user to focus on development of the test procedure (rather than on learning new opcodes of the tested CPU) allowing rapid transition from one test program development to another with minimum learning time. The controlling link is transparent to the user.

Programming

In this Configuration Panel, the board to be tested has an 80486 processor, 16-bit bus and uses 27512 type ROMs. The setting has also been specified for Reset Level and Reset Time.

The NT5000 is offered with a MS-Windows DLL library. An ATEasy driver is also available. As a standalone system, the NT5000 provides the user with an interactive set of virtual panels to access and control all of the NT5000 features. Following are examples of CPU Commander control panels:

Trigger Bus Connection Panel - The NT5000 can synchronize to other modules in the test system via the Trigger Bus.
Macro Definitions Panel - Front panel macros let you build a customized list of troubleshooting commands.
Front Panel Window - Allows the user to use the NT5000 in the interactive mode for troubleshooting or to verify the operation of the UUT.
(See figure below)

Specifications

 

NT5000

NT5100

Boot ROM Path

8 and 16 bits

8 to 32 bit

Number of PC slots

1

2

Trigger Bus

      Output

Breakpoint, SW Out
User Trigger
R/W Trigger
UUT Reset Trigger

Breakpoint, SW Out
User Trigger
R/W Trigger
UUT Reset Trigger

      Input

GP-In1, GP-In2
Status

GP-In1, GP-In2
Status

ROM Types Supported

      Size

64Kbits to 8Mbits

64Kbits to 8Mbits

      Package

28 or 32 pin DIP or PLCC. Other
styles available by special request.

28 or 32 pin DIP or PLCC. Other
styles available by special request.

Access Time

55nS or less

55nS or less

Stimuli Output

      Software
      controlled
      signals

sourcing or sinking 60mA

sourcing or sinking 60mA

      Reset
      Overdrive
      Line

Drive Current: 64mA

Drive Current: 64mA

      Level

Software selectable high and low pulse

Software selectable high and low pulse

      Pulse Width

1mS to 10S

1mS to 10S

Microprocessor Emulation Speed

Maximum rated execution speed
with no wait states

Maximum rated execution speed
with no wait states

Pod Signal Loading

100Kohm

100Kohm

Pod Cable Lengths

PC to Pod: 6 feet
Pod to ROM Socket: 1 foot

PC to Pod: 6 feet
Pod to ROM Socket: 1 foot

Number of General Purpose I/O Pins

16 bits of general purpose I/O lines; each line can be configured as input or output.

16 bits of general purpose I/O lines; each line can be configured as input or output.

Boundary Scan IEEE 1149.1 Support

One Boundary Scan Parallel/Serial Converter based on the National Semiconductor SCANPSC100F chip set. The SCANPSC100F is compatible with IEEE Std. 1149.1 JTAG Test Access Port and Boundary Scan Architecture.

One Boundary Scan Parallel/Serial Converter based on the National Semiconductor SCANPSC100F chip set. The SCANPSC100F is compatible with IEEE Std. 1149.1 JTAG Test Access Port and Boundary Scan Architecture.

System Requirements

      Hardware

486DX 33Mhz or higher

486DX 33Mhz or higher

      Memory

4 Mb, 2Mb Hard disk space, VGA Monitor,Mouse, and one 16-bit ISA slot

4 Mb, 2Mb Hard disk space, VGA Monitor,Mouse, and one 16-bit ISA slot

      Software

DOS Ver 5.0 and Windows
Ver 3.1 or higher

DOS Ver 5.0 and Windows
Ver 3.1 or higher

Connections

Two 50-pin high density connectors support two 8-bit pods or one 16-bit pod.

Ordering Information

NT5000

ROM Emulator 8/16-bit

NT5000P

ROM Emulator 8/16-bit w/logic probe

NT5100

ROM Emulator 8 to 32-bit

NT5100P

ROM Emulator 8 to 32-bit w/logic probe

NT5100-EX

Expansion kit from NT5000 to NT5100

NT6000

Diagnostic Module

ACCESSORIES

NT5200

8-bit bench pod

NT5210

8-bit testhead fixture pod

NT5220

16-bit bench pod

NT5230

16-bit testhead fixture pod

NT5300

28 Pin DIP cable

NT5310

32 Pin DIP cable

NT5320

40 Pin DIP cable (16-bit)

NT5330

32 Pin PLCC cable <1Mbit

NT5340

32 Pin PLCC cable >1Mbit

NT5350

44 Pin PLCC cable (16-bit)

NT5900-XXX

CPU Support package

NT5400

170 Pin receiver wiring cable

NT5410

170 Pin testhead wiring cable

Application Notes

App Note 23 - Dynamic Testing of Micro-Processor Based Products
App Note 27 - Design for Testability Using Emulation-Based ATE

 

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